Google

Silicon IP RTL Design Engineer, Google Cloud

Posted On

June 3, 2025

Location

Bengaluru, Karnataka

Experience Level

Freshers/Experienced

Job Type

Permanent

Apply By

June 19, 2025

Job Description

Own microarchitecture and implementation of Internet Protocols (IPs) and subsystems.
Work with Architecture, Firmware, and Software teams to drive feature closure and develop microarchitecture specifications.
Drive design methodology, libraries, debug, code review in coordination with other IPs Design Verification (DV) teams and physical design teams.
Identify and drive power, performance and area improvements for the domains owned.

Minimum qualifications:

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience
5 years of experience in ASIC development with Verilog/SystemVerilog, Vhsic Hardware Description Language (VHDL), or Chisel.
Experience with ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT).
Experience in micro-architecture and design of IPs and subsystems.

Preferred qualifications:

Experience with coding languages (e.g., Python or Perl).
Experience in System on a Chip (SoC) designs and integration flows.
Knowledge of arithmetic units, bus architectures, processor design, accelerators, or memory hierarchies.
Knowledge of high performance and low power design techniques.

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience
5 years of experience in ASIC development with Verilog/SystemVerilog, Vhsic Hardware Description Language (VHDL), or Chisel.
Experience with ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT).
Experience in micro-architecture and design of IPs and subsystems.

Google's custom-designed machines make up one of the largest and most powerful computing infrastructures in the world. The Hardware Testing Engineering team ensures that this cutting-edge equipment is reliable. In the R&D lab, you design test equipment for prototypes of our machinery and develop the protocols used to scale these tests for the entire global team. Working closely with design engineers, you give input on designs to improve our hardware until you're sure it meets Google's standards of quality and reliability.

In this role, you will be part of a team developing Application-specific integrated circuit (ASICs) used to accelerate machine learning computation in data centers. You will collaborate with members of architecture, verification, power and performance, physical design to specify and deliver quality designs for next generation data center accelerators. You will solve technical problems with micro-architecture and practical reasoning solutions, and evaluate design options with performance and power.

The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.

We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.

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