Google

Multimedia Core IP RTL Design Engineer, Silicon

Posted On

July 29, 2025

Location

Bengaluru, Karnataka

Experience Level

Freshers/Experienced

Job Type

Permanent

Apply By

Aug. 14, 2025

Job Description

Collaborate with architects and develop microarchitecture.
Perform Verilog/SystemVerilog RTL coding, functional/performance simulation debug and Lint/CDC/FV/UPF checks.
Develop RTL implementations that meet engaged power, performance and area goals.
Participate in synthesis, timing/power closure and support pre-silicon and post-silicon bring-up.
Travel to other sites across the world to collaborate with global teams.

Minimum qualifications:

Bachelor's degree in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture, or equivalent practical experience.
4 years of experience in RTL coding.
Experience with methodologies for RTL quality checks (e.g., Lint, CDC, RDC).

Preferred qualifications:

Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
Experience implementing Camera ISP image processing blocks, Video processing blocks, Machine Learning IPs, or other multimedia IPs such as Display or Video Codecs.
Experience with ASIC design methodologies for clock domain checks and reset checks.

Bachelor's degree in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture, or equivalent practical experience.
4 years of experience in RTL coding.
Experience with methodologies for RTL quality checks (e.g., Lint, CDC, RDC).

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

The gChips team develops custom silicon solutions that provide differentiated user experiences in Google Hardware products and optimize performance and power for the aimed use cases. This includes SoCs (systems on a chip) and other mixed signal, logic, and sensor ICs (integrated circuits) for our product portfolio. Working with the product teams and other teams throughout Google, gChips maps out the silicon requirements looking ahead two to four years. In addition, it ensures the Hardware Product Area is up-to-date on the latest chip technologies and CPU, IO and memory standards.

In this role, you will be part of a team that designs interconnect IP for Pixel System on a Chip (SoCs). You will collaborate with members of architecture, software, verification, power, timing, synthesis etc. to specify and deliver quality Register-Transfer Level (RTL). You will solve technical problems with micro-architecture, RTL, low power design methodology and evaluate design options with performance, power and area.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

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